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System Verilog For Verification

March 12 @ 2:00 pm - 8:00 pm


With the ever-increasing complexity of the Hardware designs to fulfill the processing requirements of today’s world, the intricacy for verification of such digital designs has become quite evident. In today’s typical System on Chip (SoC) process, the verification activities are usually the most time consuming and verification resources are generally the bottleneck. Leading SoC/ASIC/FPGA companies usually report the design to verification ratio of 1:2, which clearly shows the need of more verification engineers today and in future.

This course gives an in-depth introduction to the digital concepts in SoC verification.  This course is intended for:

•             Students of Digital Design, VLSI and Embedded Systems who want to be ready for a job in semiconductor industry.
•             Digital Design and verification professionals who are passionate to improve and always eager to learn.

The course is mainly divided in two parts. Part one focuses on the basics of the verification, challenges in typical SoC designs and different methodologies to achieve the desired goals. Second part mainly focuses on SV verification aspect to understand how object-oriented approach together with randomization and coverage collection in SV can help achieve the verification goal in a system.


March 12
2:00 pm - 8:00 pm
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RIMMS Seminar Hall
NUST, H-12
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